The hardware multiplier

Some MSP430 processors have, as a memory-mapped peripheral, a hardware 16x16->32 multiply/accumulate unit. This is accessed via eight 16-bit registers from 0x0130 to 0x013F.

Writing the first operand specifies the operation type depending on the address used:

Writing the second operand to 0x0138 starts the operation. The product is available in 0x013A(SumLo), 0x013C(SumHi) and 0x013E(SumExt) with only 2 cycles of latency. Thus, you can fetch the result with the next instruction if it's an indexed or absolute addressing mode.

If you use a register indirect or post-increment mode, you need to insert a nop (or something) between writing the second operand and reading the results.

The accumulator (SumLo and SumHi) is only 32 bits. SumExt is set to the carry (0 or 1) of the 32+32-bit sum in a MAC operation, but the old value of SumExt is not used.

In MPYS and MACS, SumExt is just the sign-extension of SumHi (0 or -1), which is not tremendously useful.

While all registers can be read back, the operation specified by the first operand's address is not recoverable by an interrupt handler. Thus, it is not possible to context-switch the multiplier unless you add some sort of wrapper software (locking or shadow registers) around it.

All registers are read/write except:

The multiplier is one 16-bit peripheral where a byte write might make sense. A byte write is zero-extended to 16 bits, which allows 8-bit unsigned operands to be used naturally.

Once the first operand has been written, multiple second operands can be written without changing it. For example, when evaluating a polynomial by Horner's rule

a + b*x + c*x^2 + d*x^3 = (((d * x + c) * x) + b) * x + a

Then x can be written to the first operand register just once.