Interrupts

The MSP430 supports 16 exception vectors, from 0xFFE0 to 0xFFFF. There are 14 maskable interrupts which are assigned to peripherals in a model-dependent way. The first 14 can be masked by clearing the GIE bit in the status register. The last two are non-maskable: 0xFFFC is the NMI vector, and 0xFFFE is the reset vector.

Actually, all of the "non-maskable" interrupt sources are maskable, just not with the GIE bit. They are:

• The RST/NMI pin can be configured to send an NMI rather than reset the processor when pulled low.

• Flash access violation.

• An oscillator fault occurs. The more recent MSP430 devices use a on chip system clock called the FLL - frequency locked loop. This can be programmed to provide a range of core clock frequencies which are phase locked to an external crystal (usually a 32kHz watch type crystal). If the frequency adjustment reaches the extreme limits, and the loop cannot lock, an oscillator fault is declared.

  Other MSP430 devices use a different oscillator module. Here the oscillator fault flag is set when one of the oscillators does not oscillate. The CPU should be using an alternate oscillator if this happens.

Handling an interrupt (other than RESET) consists of:

• Push PC on stack.

• Push SR on stack.

• Choose the highest priority interrupt to service.

• If the interrupt has only one source, reset the interrupt request bit. If there are multiple possible sources, leave them for software to poll.

• If this is an NMI, clear enable bits for the three NMI sources mentioned above.

• Clear the SR (except for SCG0), disabling interrupts and power-saving.

• Fetch the interrupt vector into the PC

• Start executing the interrupt handler

A reset is similar, but doesn't save any state.

You can nest interrupt handlers by disabling the current source and setting the GIE bit back to 1.

Note that there are no exceptions internal to the processor such as divide by zero or address error. You can cause exceptions or reset by writing to peripherals.