Low power modes

Low power operation is a key feature of the MSP430. Its design gives very low leakage, and it operates from a single supply rail. This gives an extremely low current drain when the processor is in standby mode. Several low power modes are supported, which balance the needs of different applications. As the number of the LPM mode number rises, the number of things disabled on the chip also rises:

• LPM0 - The CPU is disabled.

• LPM1 - The loop control for the fast clock (MCLK) is also disabled.

• LPM2 - The fast clock (MCLK) is also disabled.

• LPM3 - The DCO oscillator and its DC generator are also disabled.

• LPM4 - The crystal oscillator is also disabled.

As the LPM mode rises power consumption decreases, but the time needed to wake up increases. Note, however, that the MSP430's design keeps even the worst case wakeup time fairly low. For example, the parts which use the FLL system clock module need only a few microseconds to get the FLL locked after waking up.

The MSP430 is switched into a low power mode by altering bits in the status register. Typically processing within an interrupt routine will determine when the processor needs to change from a low power mode to normal operation, and alters those same status register bits to achieve that. It does this by directly modifying the memory location where the processor's status register was pushed onto the stack at the start of the interrupt. When the interrupt routine returns, using the RETI instruction, the altered status register value is loaded into the processor status register, and the processor continues operation in the newly selected mode. The C language tools support an easy method to handle this.