|mspgcc: A port of the GNU tools to the Texas Instruments MSP430 microcontrollers|
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All current MSP430s share a common memory map. The amount of each type of memory varies with the device, but the overall layout is common.
The main ROM is always at the highest addresses. In the 60K version it extends from address 0x1100 to 0xFFFF (see below for what happens between 0x1000 and 0x10FF). Some devices use mask programmed ROM or EPROM. All the more recent parts are available with flash (electrically erasable) memory, and have a mask programmed option for high volume users. If the device has flash memory, it is erasable in 512 byte pages. The device can self-program its own flash memory, although this imposes some constraints on the supply voltage.
At the low end of memory is a 512 byte space for the memory-mapped peripherals. The first 256 bytes of this are on an 8-bit bus, and can only be accessed 8 bits at a time. The second 256 bytes are on a 16-bit bus, and can only be accessed 16 bits at a time.
RAM begins at address 0x200. If there is 2K of RAM, it extends from address 0x0200 to 0x9FF.
Processors with flash memory have a 1K serial bootloader ROM at addresses 0x0C00 to 0x0FFF. This is unalterable, masked, ROM. It contains a factory set program to erase and reprogram the on board flash memory. (see later for other programming and debug options).
Processors with flash memory also have an additional 128 or 256 bytes of flash memory between addresses 0x1000 and 0x107F or 0x10FF. The only real difference between this and the main flash memory is that this is erasable in 128 byte pages. This makes it more suitable for efficiently handling configuration data.