Instruction timing

Generally, instructions take 1 cycle per word of memory accessed.

Thus, start with 1 cycle for the instruction itself. Then add 1 cycle for a memory source, 2 cycles for a memory destination, and one additional cycle per offset word.

Note that in two-operand instructions, memory destinations require an offset word, so they cost a total of 3 cycles.

This holds even for instructions (MOV, CMP and BIT) that only access the destination once.

Short immediate constants (using r2 or r3) count as register operands for instruction timing purposes.

Exceptions to this rule are:

Other CPU operations take following times to execute:

Interrupt6 cycles
Reset4 cycles